High Speed Pipelined Booth Multiplier for DSP Applications

In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of the critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is no more the speed bottleneck of a pipelined booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Besides, an 8-bit by 8-bit glitch-free Booth multiplier is pipelined as a traditional pipelined array multiplier without any bottleneck in the MBE encoder and decoder, but with better performance in both power and speed. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1 GHz in TSMC 0.35um process with a power consumption of only 100.52mw. Key-Words: Booth multiplier, MBE recoder, MBE decoder, Pipeline, DSP, Glitch-free